Water Condensation

Water Condensation

Material Name: Wafer
Record No.: 125
Primary Chemical Element in Material: Si
Sample Type: Wafer
Uses: Contamination
Etchant Name: None
Etching Method: Dry etching
Etchant (Electrolyte) Composition: No data
Procedure (Condition): No data
Note: To reduce residual end of range (EOR) damage after annealing , planar bulk CMOS junctions are sometimes implanted under "cryo " conditions, at wafer temperatures ranging from 30 to 100 °C. The resulting increase in damage accumulation from the implant results (paradoxically) in fewer residual dislocations at the junction region after thermal anneal and lower carrier recombinat ion and generation leakage currents. However, if the cold wafers are retuned to the humid clean room atmosphere before they have warmed up to near room temperature, or at least above the atmospheric dew point, water condensation can carry contaminating particles to the wafer surface in a manner similar to the problems associated with rapid pump downs in load locks.
The details of the water wetting of micron scale structures (Fig.1) depend on (1) the surface feature dimensions, (2) materials wetting angles, (3) the presence of lubricating films (4) local heat transfer rates, (5) local temperature, (6) local vapor pressure, and (7) the initiation details of droplet formation. Wit h this level of complexity, water condensation is likely to be device feature specific and difficult to predict and compensate.
Reference: Michael I. Current, Heiner Ryssel, Chapter 12, Ion Beam Purity and Wafer Contamination, ResearchGate, 2018, https://www.researchgate.net/publication/330357088, p. 33.

Figure 1: Water condensation (droplet growth (left), SEM images (right) on micron scale structure s showing wetting (W) and suspended (S) (non wetting) conditions.